Authors: MindShare Inc., Mindshare Inc, Inc Mindshare
ISBN-13: 9780201726824, ISBN-10: 0201726823
Format: Paperback
Publisher: Addison-Wesley
Date Published: November 2000
Edition: (Non-applicable)
MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.
Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.
The CD-ROM includes a 70-minute PCI-X overview video by Tom Shanley, featuring an introduction to the basic concepts underlying PCI-X bus technology. Topics covered include terminology, detection of PCI-X-capable functions, the blockoriented bus, transaction types and phases, a detailed explanation of an example transaction, and how split transactions replace the delayed transactions of PCI.
Anyone who designs or tests hardware or software that involves the PCI-X bus will find that PCI-X System Architecture is an essential resource for understanding and working with this important technology.
MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. Each title explains the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
PCI-X is the successor to the peripheral component interconnect (PCI) bus specification, the standard that enables communication between peripheral devices and the computer processor. Assuming prior knowledge of PCI, this guide describes how PCI-X achieves faster transfer rates, and details the PCI-X transaction protocol, device configuration for PCI-X, load tuning, PCI-X bridges, error detection and handling, and electrical issues. The CD-ROM contains a 70-minute PCI-X overview video. Annotation c. Book News, Inc., Portland, OR (booknews.com)
About This Book | ||
The MindShare Architecture Series | 1 | |
Cautionary Note | 2 | |
This Book Assumes PCI Background Knowledge | 3 | |
Specifications This Book Is Based On | 3 | |
Organization of This Book | 3 | |
Who This Book Is For | 4 | |
Prerequisite Knowledge | 4 | |
Documentation Conventions | 5 | |
Visit Our Web Site | 8 | |
We Want Your Feedback | 9 | |
Part 1 | Basic Concepts | |
Chapter 1 | PCI Needed Improvement | |
Chapter 2 | PCI-X Improves on PCI | |
Chapter 3 | Lowest Common Denominator Defines Mode | |
Chapter 4 | Device Types and Bus Initialization | |
Chapter 5 | PCI-X Is a Registered Bus | |
Chapter 6 | Intro to Commands | |
Chapter 7 | Intro to Transaction Phases | |
Chapter 8 | Intro to Transaction Termination | |
Chapter 9 | Intro to Split and Immediate Transactions | |
Part 2 | Transaction Protocol | |
Chapter 10 | Bus Arbitration | |
Chapter 11 | Detailed Command Description | |
Chapter 12 | Latency Rules | |
Chapter 13 | The Address, Attribute and Response Phases | |
Chapter 14 | Dword Transactions | |
Chapter 15 | Burst Transactions | |
Chapter 16 | Transaction Terminations | |
Chapter 17 | Split Completion Messages | |
Chapter 18 | 64-Bit Transactions | |
Chapter 19 | Parity Generation and Checking | |
Part 3 | Device Configuration | |
Chapter 20 | Configuration Transactions | |
Chapter 21 | Non-Bridge Configuration Registers | |
Chapter 22 | Bridge Configuration Registers | |
Part 4 | Load Tuning | |
Chapter 23 | Load Tuning Mechanisms | |
Part 5 | PCI-X Bridges | |
Chapter 24 | PCIX-to-PCIX Bridges | |
Chapter 25 | Locked Transaction Series | |
Part 6 | Error Detection and Handling | |
Chapter 26 | Error Detection and Handling | |
Part 7 | Electrical Issues | |
Chapter 27 | Electrical Issues | |
Appendix A | Protocol Rules | |
Introduction | 659 | |
General Bus Rules | 659 | |
Initiator Rules | 661 | |
Target Rules | 662 | |
Bus Arbitration Rules | 663 | |
Configuration Transaction Rules | 664 | |
Parity Error Rules | 665 | |
Bus Width Rules | 665 | |
Split Transaction Rules | 666 | |
Appendix B | Glossary | 671 |
Index | 683 |
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